In conventional substantially planar types of transistor devices a strained semiconductor layer can be used to improve transistor performance. Charge carrier mobility enhancement results from a combination of reduced effective carrier mass and reduced phonon scattering. In an n-channel metal oxide semiconductor (MOS) field effect transistor (FET) having a silicon channel improved performance can be achieved with induced biaxial tensile stress in a silicon layer along both width and length axes of an active area, or with uniaxial tensile stress along the length axis. In a p-channel MOSFET improved performance can be achieved with induced uniaxial tensile stress in the silicon layer along the width axis only (transverse tensile stress). The p-channel MOSFET can also show enhanced performance with induced uniaxial compressive stress in the top silicon layer along the length axis only (longitudinal compressive stress). Compressive stress can be provided selectively in a silicon layer, for example, by using selective epitaxial SiGe stressors in the source and drain regions of a p-channel MOSFET to induce a desired compressive stress along the length axis (longitudinal). Similarly, tensile strain can be provided, for example, by using selective epitaxial Si:C stressors in the source and drain regions of an n-channel MOSFET.
Strain engineering for three dimensional structures such as nanowires or FinFETs can be important in order to fulfill device performance requirements. However, conventional methods such as the use of an embedded source/drain (S/D) or liners are impractical for SOI FinFETs, in particular for those having small geometry gate pitches. A different approach is needed in order to further increase the strain in the channel region of the FET.